EDN

Die-to-die bonding using copper pillars

In packaging applications for cellular electronics devices, the use of flip chip copper pillar bumps has been expanding due to its better shape, lesser thickness, smaller form factor, better ...
Electronic Design

Microprobe Surpasses 1,000 Shipments for Copper Pillar Probing

MicroProbe announced today that more than 1,000 Vx and Mx vertical MEMS probe cards now are deployed worldwide in copper pillar applications. Once restricted to use in high-end logic devices, the ...
EDN

CPBs effectively blow hot and cold

The thermal copper pillar bump, or thermal bump, is a thermoelectric device made from thin-film thermoelectric material embedded in flip-chip interconnects (in particular, copper pillar bumps) for use ...
Design-Reuse

Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for copper pillar bump Flip chip version ; UMC 40nm LP LowK Logic Process

Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for copper pillar bump Flip chip version ; UMC 40nm LP LowK Logic Process ...
Electronic Design

FPGAs Get A Performance/Reliability Lift From The Bumps

According to Altera it will be the first company to use fine-pitch copper, bump-based packaging technology for commercial purposes. The technology, patented by the Taiwan Semiconductor Manufacturing ...
Semiconductor Engineering

Characterization Of Micro-Bumps For 3DIC Wafer Acceptance Tests

Custom DC positioners with theta-X planarizing capability and true Kelvin probes have allowed for successful demonstration of consistent and repeatable test results in fully automatic micro-bump wafer ...
Design-Reuse

Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY supporting 2-rank application for Copper Pillar Bump Flip Chip Version; UMC 40nm LP LVT/RVT LowK Logic Process

Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY supporting 2-rank application for Copper Pillar Bump Flip Chip Version; UMC 40nm LP LVT/RVT ...