All
Search
Images
Videos
Shorts
Maps
News
Copilot
More
Shopping
Flights
Travel
Notebook
Report an inappropriate content
Please select one of the options below.
Not Relevant
Offensive
Adult
Child Sexual Abuse
Length
All
Short (less than 5 minutes)
Medium (5-20 minutes)
Long (more than 20 minutes)
Date
All
Past 24 hours
Past week
Past month
Past year
Resolution
All
Lower than 360p
360p or higher
480p or higher
720p or higher
1080p or higher
Source
All
Dailymotion
Vimeo
Metacafe
Hulu
VEVO
Myspace
MTV
CBS
Fox
CNN
MSN
Price
All
Free
Paid
Clear filters
SafeSearch:
Moderate
Strict
Moderate (default)
Off
Filter
12:39
Logic synthesis | verilog logic synthesis(Part1)
4.7K views
Jun 25, 2020
YouTube
Explore Electronics
7:56
Simulation, Synthesis and Design methodology in Verilog | #4 | Veril
…
48.6K views
Jun 29, 2021
YouTube
VLSI POINT
31:25
SYNTHESIZABLE VERILOG
31.7K views
Sep 13, 2017
YouTube
Hardware Modeling Using Verilog
16:33
DVD - Lecture 4e: Verilog for Synthesis - revisited
6.9K views
Oct 14, 2022
YouTube
Adi Teman
6:25
xilinx vivado Tutorial 2 | how to do verilog Synthesis in Xilinx Vivado
…
10.4K views
Jul 10, 2021
YouTube
Explore Electronics
29:29
DVD - Lecture 2b: Verilog Syntax
18.7K views
Oct 12, 2022
YouTube
Adi Teman
13:10
DVD - Lecture 3a: Logic Synthesis - Part 1
19.7K views
Oct 13, 2022
YouTube
Adi Teman
34:45
RTL2GDS Demo Part 2.1: Synthesis with Genus
5.2K views
Feb 25, 2025
YouTube
Adi Teman
3:58
How to Synthesize Verilog HDL in Quartus Prime (OSU ECE272)
4K views
Nov 3, 2022
YouTube
Jacob Field
34:52
How to write Synthesizeable RTL
26.8K views
Dec 13, 2021
YouTube
Adi Teman
1:08:06
Mastering Verilog in 1 Hour 🚀: A Complete Guide to Key Concepts
…
72K views
Mar 9, 2025
YouTube
Explore VLSI
6:10
DVD - Lecture 2a: Verilog
18.5K views
Oct 12, 2022
YouTube
Adi Teman
1:21:05
System Verilog Simplified: Master Core Concepts in 90 Minutes!"🚀: A
…
31.3K views
1 year ago
YouTube
Explore VLSI
1:00
NOR Gate in Verilog | Gate, Dataflow & Behavioral | EDA Playground #v
…
694 views
5 months ago
YouTube
Maharshi Sanand Yadav T
2:21:17
Verilog in 2 hours [English]
218K views
Jul 23, 2020
YouTube
Renzym Education
10:03
DVD - Lecture 1a: Introduction
110.3K views
Oct 12, 2022
YouTube
Adi Teman
21:07
DVD - Lecture 2d: Verilog FSM Implementation
14.5K views
Oct 12, 2022
YouTube
Adi Teman
42:03
Introduction to Verilog HDL using Free Software Icarus, GTKWave, a
…
81.4K views
Apr 25, 2022
YouTube
boyfriendnibluefairy
2:59:09
Verilog in One Shot | Verilog for beginners in English
67.4K views
May 31, 2024
YouTube
VLSI POINT
10:01
How to download, install and use Xilinx Vivado 2025 Tool for FREE
…
24.9K views
6 months ago
YouTube
Explore VLSI
51:31
Verilog HDL Basics
5.2K views
Oct 18, 2024
YouTube
Altera
3:43
what is parsing in VLSI || Synthesis and STA || #STA || #Synthesisand
…
162 views
10 months ago
YouTube
Maharshi Sanand Yadav T
8:11
Mastering Verilog: Modules, Ports & Data Types (Wire, Reg, Logic) | Pa
…
38 views
5 months ago
YouTube
Crack the Electronics with Rajesh
6:36
Introduction to Verilog HDL | VLSI | Verilog HDL Tutorial in Urdu/Hindi
48.5K views
Oct 10, 2020
YouTube
Electro DeCODE
28:41
(Sponsored) FPGA Design Tutorial (Verilog, Simulation, Implementati
…
119.8K views
May 31, 2023
YouTube
Phil’s Lab
7:06
Simulation, Synthesis and Design methodology in Verilog | #4 | Veril
…
37.7K views
Jun 25, 2021
YouTube
VLSI POINT
2:01:33
DVD - Lecture 5: Timing (STA)
102.2K views
Dec 8, 2018
YouTube
Adi Teman
49:01
(Part -3) Digital logic SYNTHESIS || why synthesis || Synthesis flow ||
…
7.4K views
Jul 13, 2021
YouTube
Component Byte
20:27
How to implement Logic Gates on FPGA | 100 Days of FPGA
1.6K views
5 months ago
YouTube
The Hardware Developer
14:41
DVD - Lecture 2c: Simple Verilog Examples
12.5K views
Oct 12, 2022
YouTube
Adi Teman
See more videos
More like this
Feedback